字典二二>英语词典>instruction execution翻译和用法

instruction execution

英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

网络  指令执行

计算机

英英释义

noun

  • (computer science) the process of carrying out an instruction by a computer
      Synonym:execution

    双语例句

    • Characteristics of the microprocessor are fast speed and nimble instructions. The way of raising speed is to adopt pipelining in instruction execution.
      它的运算速度提高的途径是指令的执行采用流水线方式,指令缓冲部件IB采用两个体交替接收指令和执行指令的办法来减少取指令的等待时间。
    • The Digital Signal Processing which is regarded as CPU on board has some advantages, such as fast instruction execution, high bus bandwidth, and high speed real-time data processing.
      数据采集卡部分使用使用DSP来作采集卡CPU具有指令执行速度快、总线带宽高、可以完成数据的高速实时处理等优点。
    • Research and Analysis of the Value Prediction and Instruction Reuse Techniques in Speculated Execution
      推测执行中值预测与指令重用技术的研究与分析
    • The platform introduces two memory system structure, addressing mode simulation guarantees that not only the operand is correctly obtained, but also the instruction execution time is correctly calculated.
      采用了两种存储器体系结构,寻址方式的模拟不仅保证了正确地确定操作数,而且能够正确统计指令执行时间。
    • But in reality, the upper software drives the underlying hardware, for example different instruction execution and data access affect the underlying hardware circuit directly and result in different power generation.
      但在实际情况中,底层硬件受上层软件驱动,例如不同指令执行和数据存取等软件指令直接影响底层硬件的电路活动,导致不同功耗产生。
    • A4-stage instruction pipeline for instruction execution makes at-speed test possible.
      四级指令流水线的引入使全速测试成为可能。
    • Bochs was developed purely in the C++ language for interpreted x86 instruction execution and platform emulation.
      对于解译的x86指令执行和平台仿真,Bochs完全是用C++语言开发的。
    • This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
      本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系,并分析了新型超标量RISC结构的实现方案,其中包括具有单个执行部件和多个执行部件的结构。
    • Pipeline is dealing with instruction, including instruction decode, issue, and execution.
      流水线正在处理指令,包括指令解码、发布和执行。
    • In the traditional Cache, the Cache hit ratio is insured only by the address locality of memory reference instruction stream during program execution, it restricts the improvement of Cache hit ratio.
      在传统的Cache中,仅仅依靠程序执行时访存指令流地址的局域性来保证较高的Cache命中率,使得Cache命中率的提高受到限制。